1. Field of the Invention
The present invention relates to techniques for reducing power consumption in an integrated circuit (IC) chip. More specifically, the present invention relates to a method and apparatus for reducing power consumption of the IC chip by judiciously placing the standard cells in the IC chip.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, onto a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
However, as the clock frequency of these systems increases, power consumption also increases. In addition to meeting timing and area constraints, power consumption is becoming an important concern for designers of integrated circuits. Excessive power consumption can cause problems in dissipating heat. Additionally, to prolong battery life used in mobile devices such as laptops, cell phones, PDAs, and MP3 players, power consumption must be reduced.
Power consumption can be divided into several components: net-switching power, leakage power, and cell internal power. Net-switching power is the power consumed when switching a net from one state to another one. At the present time, net-switching power accounts for the majority of the power consumption in an integrated circuit chip.
A large component of net-switching power comes from clock nets because clock nets switch during every cycle. Furthermore, the clock tree has a large load because it drives all of the registers and the clock lines feeding the registers. The power consumed on these clock nets is proportional to k*V2C*f, where k is a constant, V is the supply voltage, C is the capacitance of the net and the load connected to the net, and f is the switching frequency of the signal. As the frequency increases or the capacitance increases, power consumption increases. This net-switching power can be somewhat mitigated by decreasing the supply voltage, but this technique has limitations because as supply voltage is decreased, the transistors will run out of headroom and noise margin. The invention reduces C*f, the product of the capacitance and the switching frequency.
A small amount of power consumption within a cell occurs when a temporary short-circuit path between VDD to ground exists. For instance, when an inverter circuit switches from high-to-low or low-to-high, for a brief time interval during the transition, the pull-up device and the pull-down device are both conducting, which causes the inverter circuit to consume a large amount of power. This power consumption component can be somewhat mitigated by sizing the transistors to trade-off performance for decreased power consumption.
In addition to the power management techniques mentioned above, It is possible to turn off the clock in the unused sections of the chip, which can significantly reduce power consumption. It is also possible to reduce or cut off the voltage supply to the sections of the chip not being used. However, when these sections of the chip are active, net-switching power is still being consumed.
Even if all of the above-described techniques are used, power consumption still remains a problem. Hence, what is needed is a method and an apparatus to reduce power consumption in an integrated circuit chip even further.